Managing yield in highly integrated semiconductor designs is a very important problem. Most large chips contain scan chains to support testing the chip and diagnosing problems should those tests fail. Scan chains enable the observation of functional logic in the chip by latching onto results of the functional logic and serially scanning the results out. If the chip is defective and the defect does not affect the scan chains, then traditional diagnostic techniques can be used to isolate the defect and determine the manufacturing or design problem that caused the defect. This problem can often be fixed to prevent future chips from having the same defect. When this process is applied over time, the percentage of good chips from a manufacturing batch can rise, the cost of good chips becomes lower, and the time-to-volume production can be decreased.
However, when a defect on a chip renders one or more of its scan chains nonfunctional, traditional diagnostics techniques fail, and yield management becomes a more difficult process. Given that scan chain logic covers only ten to twenty percent all the logic on a chip, a random defect will break the scan chain only ten or twenty percent of the time, leaving eighty to ninety percent of the chips for which traditional techniques can be applied. However, in the early stages of manufacturing and technology development, where the yield management process is often most important, it is likely that any given chip may be affected by more than one defect. Thus, the percentage of chips which have nonfunctional scan chains becomes higher, possibly up to fifty percent of all chips. At this point, the capability to isolate a defect, even when scan chains are defective, becomes vital.
Although several methodologies have been developed to isolate a defect in a scan chain failure, these methodologies have many drawbacks.
One technique is to fault simulate the entire scan process, and use traditional diagnostic techniques to isolate the failure. The problem with this technique is that fault simulation of the entire scan process is too costly in terms of CPU and elapsed time.
Another technique is to generate special test patterns that are designed to isolate a failure in the scan chain. The problem with this technique is that generation of special test patterns requires special processing that is out of the standard manufacturing process.
Another technique is to perform “good machine” simulation of the non-scan parts of the test, assuming that the defect is at a specific bit, and modifying the values in the scan latches to be consistent with that assumption. The problem with this technique is that performing “good machine” simulation requires guessing where the defect occurs. Multiple simulations are required to identify which guess is the best guess. Since it is not cost-effective to simulate a defect at each bit in the scan chain, heuristics are required to identify the best guess. These heuristics trade off accuracy for run-time. Another deficiency of this technique is that it can typically isolate a defect only down to the path from one scan bit to the next scan bit. Typically, a more granular isolation is required.
Accordingly, there is a need for techniques for isolating defects in scan chains quickly and accurately, and which avoid drawbacks of the prior art.